FIG. 5 is a diagram depicting an example of a slope voltage generating circuit in a conventional current mode control type switching regulator (for example, see Patent Document 1). In the current mode control type switching regulator, an inductor current iL flowing through an inductor when a switching transistor is on is the same as a drain current of the switching transistor. When on-resistance of the switching transistor is known, the inductor current iL can be detected by detecting a voltage drop caused by the switching transistor.
In view of this, an inductor current detecting circuit 110a detects a voltage drop caused when the switching transistor is on. When the switching transistor is on, a gate signal S101 supplied to the switching transistor is at a low level. At this time, a PMOS transistor M113 is turned on at the same time as a PMOS transistor M112 is turned off. Therefore, a voltage VLx of a node Lx between the switching transistor and the inductor is inputted to a non-inverting input terminal of an operational amplifier circuit 111.
The operational amplifier circuit 111 controls a gate voltage of a PMOS transistor M111 so that a source voltage of the PMOS transistor M111 becomes the same voltage level as the voltage VLx. Therefore, a drain current of the PMOS transistor M111 is proportional to the inductor current iL. The drain current is converted into a voltage VA by a resistor R112. The voltage VA is outputted through a resistor R113. When the resistors R111 and R112 have the same resistance values, the source voltage VA of the PMOS transistor M111 is expressed by a formula (a) below.VA=Vin−VLx  (a)
Further, when the switching transistor is off, the gate signal S101 is at a high level. In this case, the PMOS transistor M113 is turned off at the same time as the PMOS transistor M112 is turned on. Therefore, an input voltage Vin is inputted to the non-inverting input terminal of the operational amplifier circuit 111. Since the operational amplifier circuit 111 turns off the PMOS transistor M111, the source voltage VA of the PMOS transistor becomes 0 V. An NMOS transistor M114 of a ramp voltage generating circuit 110b is on and conductive during a period when the gate signal S101 is at a high level. Therefore, a current i113 outputted from the constant current circuit 113 is bypassed to the NMOS transistor M114. As a result, a terminal voltage VB of a ramp capacitor C111 is 0 V.
Subsequently, when the gate signal S101 is at a low level, the NMOS transistor M114 is turned off and nonconductive. Therefore, the ramp capacitor C111 is charged by the output current i113 of the constant current circuit 113. A terminal voltage VB of the ramp capacitor C111 is linearly increased to generate a ramp voltage. The ramp voltage VB is outputted through a resistor R114. Output voltages of the inductor current detecting circuit 110a and the ramp voltage generating circuit 110b are added by the resistors R113 and R114 and outputted from a node between the resistors R113 and R114. The resistors R113 and R114 have the same resistance values. When a voltage of the node between the resistors R113 and R114 is VC, the voltage VC is expressed by a formula (b) below.VC=(VA+VB)/2=(Vin−VLx+VB)/2  (b)
The voltage VC in the above formula (b) is inputted to a non-inverting input terminal of an operational amplifier circuit 114 in an offset voltage generating circuit 110c. The operational amplifier circuit 114 controls a gate voltage of an NMOS transistor M116 so that a source voltage of the NMOS transistor M116 becomes the same voltage level as the voltage VC. As a result, a drain current of the NMOS transistor M116 is proportional to the voltage VC. The drain current is supplied to a resistor R117 through a current mirror circuit formed of PMOS transistors M117 and M118. The drain current is converted into a voltage by the resistor R117 to be an output voltage Vslp of the slope voltage generating circuit 110.
However, the resistor R117 also receives a current supply from a constant current circuit 115 in addition to the output current of the current mirror circuit. Therefore, an offset voltage (r117×i115) corresponding to a voltage obtained by multiplying an output current i115 of the constant current circuit 115 with a resistance value r117 of the resistor R117 is added to the output voltage Vslp of the slope voltage generating circuit 110. In the case where the resistors R116 and R117 have the same resistance values and the resistance value of the resistor R117 is r117, the output voltage Vslp of the slope voltage generating circuit 110 is expressed by a formula (c) below.
                                                        Vslp              =                            ⁢                              VC                +                                  (                                      r                    ⁢                                                                                  ⁢                    117                    ×                    i                    ⁢                                                                                  ⁢                    115                                    )                                                                                                        =                            ⁢                                                                    (                                          Vin                      -                      VLx                      +                      VB                                        )                                    /                  2                                +                                  (                                      r                    ⁢                                                                                  ⁢                    117                    ×                    i                    ⁢                                                                                  ⁢                    115                                    )                                                                                        (        c        )            
Note that (r117×i115) in the formula (c) indicates the offset voltage.
Patent Document 1: Japanese Laid-Open Patent Application No. 2006-246626
However, poor linearity in a rising part of the slope voltage Vslp has been a problem in the slope voltage generating circuit 110 shown in FIG. 5. FIG. 6 is a diagram showing a waveform example of the slope voltage Vslp generated by the slope voltage generating circuit 110. As shown in FIG. 6, the slope voltage Vslp rises gently right after the gate signal S101 becomes a low level, and the inclination gradually approaches a proper inclination over time. When a time Tdel passes after the gate signal S101 becomes a low level, the slope voltage Vslp rises with the proper inclination.
The slope voltage Vslp rises gently due to a delay time caused when the voltage VC is converted into a current by a voltage-current converter circuit of the operational amplifier circuit 114 and a delay time caused by the current mirror circuit formed of the PMOS transistors M117 and M118. When the slope voltage Vslp rises gently, the operation of the switching regulator becomes unstable in such cases where there is a large difference between the input voltage Vin and an output voltage Vo of the switching regulator, in which case an on-time of the switching transistor becomes shorter than the time Tdel. As a result, a defect may be caused in that the output voltage Vo becomes unstable, and the like.